For typical switching mode power converters of the prior art, the output voltage is controlled by an electronic circuit which measures a level of the output voltage, compares that measured level to a predetermined desired level, and develops a response to that measurement elsewhere in the circuit in order to more accurately achieve the desired output voltage. A prior art switching mode power converter which uses a trailing edge modulation control scheme is illustrated in FIG. 1. The input voltage Vin is coupled to a first terminal of the inductor L1. A second terminal of the inductor L1 is coupled to a first terminal of a switch SW1 and to an anode of a diode D1. A capacitor C1 is coupled between a cathode of the diode D1 and a second terminal of the switch SW1. A load RL is coupled across the capacitor C1. A potentiometer PT1 is coupled across the load RL and provides a negative input of a voltage error amplifier 10. A reference voltage Vref1 is coupled to the positive input of the error amplifier 10. The output VEAO of the voltage error amplifier 10 is coupled as the positive input of a modulating comparator 14. The negative input of the modulating comparator 14 is coupled to receive the ramp output of an oscillator 12. The output of the modulating comparator 14 is coupled as the reset input R of a flip-flop 16. The input D of the flip-flop 16 is coupled to the inverted output Q of the flip-flop 16. A clock input CLK of the flip-flop 16 is coupled to the clock output of the oscillator 12. The output Q of the flip-flop 16 is coupled to control the operation of the switch SW1.
The output voltage Vout1 supplied to the load RL is formed by integrating the inductor current I1 in the capacitor C1. Pulse width modulation (PWM) is used to maintain a constant output voltage Vout1 when the input voltage Vin or current drawn by the load RL varies over time. By modulating the width of voltage pulses that control the switch SW1, the output voltage Vout1 can be maintained at a constant level. Energy from the input source Vin is stored in the inductor L1 when the switch SW1 is closed. When the switch SW1 is open, energy from the inductor L1 is transferred to the capacitor C1 and to the load RL. A predetermined fraction of the output voltage Vout1 is formed by the potentiometer PT1. This voltage VEA is input into the negative terminal of the error amplifier 10 for comparison to the reference voltage Vref1. The comparison determines how close the actual output voltage Vout1 is to the desired output voltage and is used to modulate the width of the pulses that control the switch SW1.
FIG. 1 illustrates a trailing edge pulse width modulation scheme for controlling the switch SW1. In trailing edge modulation, the switch SW1 turns on (closes) on the trailing edge of the clock signal. The leading edge of the clock signal may also be utilized to implement leading edge modulation. For a leading edge modulation control scheme, the inputs to the error amplifier 10 are reversed: the voltage VEA from the potentiometer PT1 is coupled to the positive terminal of the voltage error amplifier 10 and the reference voltage Vref1 is coupled to the negative terminal of the voltage error amplifier 10. Also, the control voltage VSW1 is taken directly from the output Q of the flip-flop 16.
FIGS. 2, 3 and 4 show corresponding voltage waveforms with respect to time of different voltage levels at different points within the switch control circuit 18 of the trailing edge scheme, illustrated in FIG. 1. The time axis for the FIGS. 2, 3 and 4 has been drawn to correspond in all three figures. FIG. 2 illustrates the voltage levels with respect to time of the error amplifier output VEAO and the modulating ramp output of the oscillator 12. FIG. 3 illustrates the voltage level of the control voltage VSW1 for the switch SW1 with respect to time. The switch SW is "on" or closed when the control voltage VSW1 is at a high voltage level. The switch SW1 is "off" or open when the control voltage VSW1 is at a low voltage level. FIG. 4 illustrates the clock impulses with respect to time of the clock output of the oscillator 12.
The switch SW1 will turn on after the trailing edge of the system clock. Once the switch SW1 is on, the modulating comparator 14 then compares the error amplifier output voltage VEAO and the modulating ramp. When the modulating ramp reaches the error amplifier output voltage, the output of the modulating comparator 14 will fall to a logical low voltage level. Because of the inverter coupled to the input, the input R of the flip-flop 16 will then rise to a logical high voltage level thereby resetting the output Q of the flip-flop 16 to a logical low voltage level and turning the switch SW1 off. When the switch SW1 is on, the inductor current IL will ramp up. The effective duty cycle of the trailing edge modulation is determined as a ratio of the on time of the switch SW1 to its off time. FIG. 1 illustrates a typical trailing edge control scheme using a single boost power converter stage. As the input voltage Vin or current drawn by the load RL vary over time, the duty cycle or time that the switch SW1 is on will vary in order to maintain a constant output voltage Vout1.
While the above-described circuit regulates the output voltage Vout1, it does not ensure that the input current follows the input voltage in time and amplitude proportionally. When a power converter such as in shown in FIG. 1 is coupled to receive a rectified line voltage, it can cause problems in a power distribution system, such as reducing the capacity of the distribution system, increasing harmonics and overheating substation transformers. Therefore, it is desirable that a power converter ensure that the input current follow the line voltage such that the power converter is substantially a resistive load to the power line. A power factor correction circuit ensures that the input current follows the line voltage in time and amplitude proportionally (i.e. the input voltage and current are maintained in phase relative to each other).
A circuit diagram of a prior art boost rectifier circuit including pulse width modulation and power factor correction (PFC) is illustrated in FIG. 5. A line voltage is coupled to the input terminals of a full wave bridge rectifier 20. A first output terminal of the full wave bridge rectifier 20 is coupled to a first terminal of an inductor L2 and to a first input terminal of a multiplier 22. A second terminal of the inductor L2 is coupled to a drain of an NMOS transistor SW2 and to an anode of a diode D2. A source of the NMOS transistor SW2 is coupled to the ground node.
A cathode of the diode D2 is coupled to a first terminal of a capacitor C2 and to an output node Vout2. A second terminal of the capacitor C2 is coupled to the ground node. A first terminal of a resistor R1 is coupled to the output node Vout2. A second terminal of the resistor R1 is coupled to a negative input of an output voltage error amplifier 24 and to a first terminal of a resistor R2. A second terminal of the resistor R2 is to the ground node. A positive input of the voltage error amplifier 24 is coupled to a reference voltage Vref2. An output of the voltage error amplifier 24 is coupled to a second input of the multiplier 22.
An output of the multiplier 22 is coupled to a positive input terminal of a current error amplifier 26 and to a first terminal of a resistor Ra. A second terminal of the resistor Ra is coupled to a second output terminal of the full wave bridge rectifier 20 and to a first terminal of a sense resistor Rs. A second terminal of the sense resistor Rs is coupled to a first terminal of a resistor Rb and to the ground node. A second terminal of the resistor Rb is coupled to a negative input terminal of the current error amplifier 26. An output of the current error amplifier 26 is coupled to a negative input terminal of a modulating comparator 28. A ramp output of an oscillator 30 is coupled to a positive input terminal of the modulating comparator 28. An output of the modulating comparator 28 is coupled as an input R of a flip-flop 32. A clock output of the oscillator 30 is coupled as an input S of the flip-flop 32. An output Q of the flip-flop 32 is coupled to a gate of the NMOS transistor SW2.
A signal from the full wave bridge rectifier 20 is applied to one of the inputs of the multiplier 22. The other input of the multiplier 22 is the output of the voltage error amplifier 24. The multiplier 22 is usually of a current input type which enables the multiplier 22 to have greater ground noise immunity.
The output of the multiplier 22 is a current which is the product of the reference current, the output of the voltage error amplifier 24 and a gain adjustment factor. This output current is applied to the resistor Ra. The voltage across the resistor Ra subtracts from the sensed voltage across the sense resistor Rs and is applied to the current error amplifier 26. Under closed loop control, the current error amplifier 26 will try to keep this voltage differential near the zero volt level. This forces the voltage produced by the return current flowing through the sense resistor Rs to be equal to the voltage across the resistor Ra.
The amplified current error signal output from the current error amplifier 26 is then applied to the negative input of the modulating comparator 28. The other input of the modulating comparator 28 is coupled to receive the ramp signal output from the oscillator 30. Pulse width modulation is obtained when the amplified error signal that sets up the trip point modulates up and down.
Thus, a current control loop modulates the duty cycle of the switch SW2 in order to force the input current to follow the waveform of the full wave rectified sinewave input voltage. The current control loop and the power delivery circuitry must have at least enough bandwidth to follow this waveform.
The above-described power factor correction circuit is a switching mode power converter. Like other switching mode converters, it too, may cause problems in a power distribution system such as large harmonic currents, excessive neutral current, hot spots in a transformer and voltage distortion. Thus, it is desirable to include a second power converter stage to reduce harmonic currents. For example, the output voltage formed by the power factor correction circuit illustrated in FIG. 5 can be utilized as the input voltage Vin of the pulse-width modulation stage illustrated in FIG. 1, thus, forming a combination PFC-PWM power converter.
A drawback to such a combination PFC-PWM power converter is that the switch SW1 in the pulse-width modulation stage and the switch SW2 in the power factor converter stage are both continuously switching at appropriate duty-cycles. Therefore, the PFC-PWM power converter is continuously drawing power. A load coupled to the receive the output voltage Vout1 from the pulse-width modulation stage, however, can require a relatively low current at various times, depending upon the requirements of the load. Therefore, what is needed is a switching regulator that is responsive to the power consumption requirements of the load in order to conserve energy.